A PLL is a frequency-selective feedback system that is capable of synchronizing with an applied input signal and tracking frequency changes associated therewith. PLLs are used in a wide variety of applications, including, but not limited to, frequency synthesizers, clock and data recovery circuits, and communications systems. FIG. 1 illustrates a basic analog PLL 100 comprising four functional blocks, namely, a phase detector 102, a charge pump 104, a loop filter 106, and a voltage-controlled oscillator (VCO) 108. These four blocks 102, 104, 106, 108 are interconnected in a feedback arrangement as shown. The phase detector 102 compares the phase φIN of a reference input signal Vs(t) with a phase φVCO of an output signal generated by the VCO 108, and generates an error signal Ve(t). This error signal Ve(t) typically consists of either an UP pulse (when φIN leads φVCO) or a DOWN pulse (when φIN lags φVCO) where the error signal Ve(t) represents a difference between φIN and φVCO. The charge pump 104 generates an amount of charge based on the error signal Ve(t), where the sign of the charge indicates the direction of UP or DOWN.
Depending on whether the error signal Ve(t) was an UP pulse or a DOWN pulse, the charge is either added to or subtracted from, respectively, a capacitance (not shown) in the loop filter 106. Thus, the loop filter 106 functions as an integrator which accumulates the net charges from the charge pump 104. The resulting loop filter voltage Vc(t) is applied to a control input of the VCO 108 for varying the frequency of the output signal generated by the VCO. The basic theory and principle of operation of PLLs are well known, as described, for example, in Alan B. Grebene, “Bipolar and MOS Analog Integrated Circuit Design,” pp. 627-678, John Wiley & Sons, 1984, and Dan H. Wolaver, “Phase-Locked Loop Circuit Design,” Prentice Hall, N.J., 1991, which are incorporated herein by reference, and therefore not further described herein.
One disadvantage of analog PLLs is that capacitors in the loop filter for accumulating the charge generated by the charge pump often consume a relatively large area in an integrated circuit in which the PLL may be implemented, especially compared to digital circuitry which is often integrated with the PLL. Furthermore, the area consumed by the loop filter capacitors generally does not scale with advances in integrated circuit process technology, making it difficult to reduce the size of the analog PLL. Previous attempts to reduce the size of analog PLLs have involved reducing the charge pump current in order to reduce the size of the capacitors in the loop filter. However, this approach provides only a slight savings in area. Moreover, reducing the charge pump current can significantly increase the susceptibility of the PLL to noise, and therefore undesirably increase jitter in an output signal produced by the PLL.
In order to overcome some of the problems inherent in analog PLLs, it is well known to employ digital PLLs (DPLLs). In a conventional DPLL, the charge pump, loop filter and analog VCO are typically replaced with a digital implementation thereof. By eliminating the large capacitors associated with the loop filter, a substantial savings in integrated circuit area can be achieved. However, most DPLLs exhibit an undesirable phenomenon often referred to as “hunting.” Hunting results, at least in part, from quantization errors in the digital VCO and/or VCO control voltage, and may cause jitter in the output signal generated by the PLL. Because the output signal of the digital VCO is limited to certain discrete frequencies, a feedback control loop in the DPLL will often overcompensate for the frequency mismatch between the output signal of the VCO and the input reference signal by causing the VCO to continuously speed up and slow down (i.e., “hunt”) as the DPLL attempts to match its output to the input reference signal.
There exists a need, therefore, for an improved PLL that does not suffer from one or more of the problems exhibited by conventional PLL arrangements.